1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which a bit line of a memory cell is precharged in a data read operation.
2. Description of the Related Art
An asynchronous semiconductor memory has been known in which a bit line of a memory cell begins to be precharged when a transition to a next address is detected, and data is read after the precharging is completed (see FIG. 1 of Japanese Patent Kokai No. 2003-85970 (Patent Literature 1) as an example). In this semiconductor memory, an address transition detection (ATD) circuit detects whether a transition to a next address has been made, and generates an address change detection signal ATD as a result of the detection. A precharge enable signal PE is generated based on the address change detection signal ATD, and precharging is performed with respect to a bit line of a memory cell corresponding to the next address in response to the precharge enable signal PE (see FIGS. 1 and 3 of Patent Literature 1 as an example).
Here, when the transition to the next address is made, a period in which addresses change and are thus unsettled (referred to hereinafter as an “address skew period”) is present immediately before the “next address” is reached, by the influence of an address skew. As a result, if the address skew period is relatively long, in response to the precharge enable signal PE, precharging is sequentially carried out with respect to respective bit lines corresponding to a group of unsettled addresses appearing in the address skew period and, successively, precharging to be originally carried out is performed with respect to the bit line corresponding to the “next address”. At this time, provided that one adjacent to the bit line corresponding to the “next address” is present among the respective bit lines corresponding to the group of unsettled addresses, coupling noise may accompany a cell recovery operation through the bit lines corresponding to the unsettled addresses, resulting in there being a concern that erroneous data reading could be carried out.
Therefore, in the case where the aforementioned semiconductor memory is employed as a random access memory (RAM) to be used in a board in which an information processing system is constructed, an address skew period allowed in the board needs to be equal to or shorter than an address skew period specified in the semiconductor memory. That is, provided that the address skew period allowed in the board is longer than the address skew period specified in the semiconductor memory, there may be a concern that erroneous data reading could be carried out, resulting in a problem that this semiconductor memory may not be equipped on the board.